There are drawbacks associated with traditional 64-bit scaled sum-of-product operations. In traditional 64-bit scaled sum-of-product operations, scaling operations and sum-of-product operations may need to be performed separately, which may increase the number of instructions needed for such operations (and, therefore, the number of cycles associated with executing such operations). Other traditional 64-bit scaled sum-of-product operations may require 64-bit adders and 64-bit registers (or 32-bit register pairs) or, where such adders are unavailable, multiple microcycles using 32-bit adders. Such operations may, however, decrease silicon efficiency, adversely affect processor performance, or both.